TechTechPotato | [36] TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA @TechTechPotato | Uploaded July 2024 | Updated October 2024, 4 hours ago.
Over the past year, I’ve had the chance to quiz every major foundry about their plans for the future. The latest in this series is TSMC, as part of their recent announcements around their roadmaps and upcoming process node technologies. As the world’s leading manufacturer of leading edge and EUV-based logic, as well as packaging the vast majority of the big AI chips, the pressure on TSMC to execute at speed and scale has only increased over the last few years. As part of their commitments to next-generation technologies, the company announced its A16 process node, Super Power Rail (the marketing name for its backside power delivery), ventures into co-packaged optics, and Silicon-on-Wafer technology, leveraging a demand for bigger substrates for the biggest chips. Here’s my latest video on these announcements.
youtube.com/watch?v=isjeYKLBffs
These announcements were made at TSMC’s US Technology Symposium earlier this year. The symposium is a roadshow, covering continents and key markets for the company. Just before the EU Symposium, I had a chance to catch up with Dr. Kevin Zhang, SVP and Deputy Co-COO of TSMC for an interview. We covered a wide range of topics, from Kevin’s thoughts on Moore’s Law, to how the market has changed under the weight of AI (also, the activations of AI).
[00:00] Intro
[00:48] Q: Is Moore's Law Dead?
[02:11] Q: The utility of incremental manufacturing nodes
[03:37] Q: Customer's leveraging node upgrades
[04:24] Q: How many of the advancements are customer or internally driven?
[05:43] Q: What do A16 and SPR bring to the table?
[08:07] Q: Does adding SPR increase cost per transistor?
[08:37] Q: Are A16 and SPR a package deal?
[09:15] Q: Where in the development cycle are A16 & SPR?
[10:16] Q: How different is NanoFlex from FinFlex?
[12:37] Q: How is the scale up of CoWoS progressing?
[15:59] Q: How do you plan to cool these massive chips?
[16:47] Q: When are you expecting SoW to be in production?
[17:08] Q: Due to new optics shrinking reticle sizes, will you reduce this too?
[17:32] Q: What are the current limits in semiconductors?
[18:59] Q: What is TSMC COUPE?
[21:33] Q: Which approach is best in optical?
[22:24] Q: Does TSMC have any plans for pluggable optics?
[23:15] Q: What are TSMC's plans for High-NA EUV?
[25:06] Q: How are the plans for the fab expansions going?
[26:48] Q: Does that extend to packaging?
[27:08] Q: What effects has the AI Boom had on your R&D decisions?
[28:15] Wrap-up
[29:07] Outro
Written version: open.substack.com/pub/morethanmoore/p/q-and-a-with-tsmc-on-next-gen-foundry
-----------------------
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Ending music: youtube.com/watch?v=2N0tmgau5E4
-----------------------
Welcome to the TechTechPotato (c) Dr. Ian Cutress
Ramblings about things related to Technology from an analyst for More Than Moore
#tsmc #a16 #bspdn
------------
More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Armari, ASM, Ayar Labs, BCG, Baidu, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NordPass, NVIDIA, ProteanTecs, Qualcomm, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.
Over the past year, I’ve had the chance to quiz every major foundry about their plans for the future. The latest in this series is TSMC, as part of their recent announcements around their roadmaps and upcoming process node technologies. As the world’s leading manufacturer of leading edge and EUV-based logic, as well as packaging the vast majority of the big AI chips, the pressure on TSMC to execute at speed and scale has only increased over the last few years. As part of their commitments to next-generation technologies, the company announced its A16 process node, Super Power Rail (the marketing name for its backside power delivery), ventures into co-packaged optics, and Silicon-on-Wafer technology, leveraging a demand for bigger substrates for the biggest chips. Here’s my latest video on these announcements.
youtube.com/watch?v=isjeYKLBffs
These announcements were made at TSMC’s US Technology Symposium earlier this year. The symposium is a roadshow, covering continents and key markets for the company. Just before the EU Symposium, I had a chance to catch up with Dr. Kevin Zhang, SVP and Deputy Co-COO of TSMC for an interview. We covered a wide range of topics, from Kevin’s thoughts on Moore’s Law, to how the market has changed under the weight of AI (also, the activations of AI).
[00:00] Intro
[00:48] Q: Is Moore's Law Dead?
[02:11] Q: The utility of incremental manufacturing nodes
[03:37] Q: Customer's leveraging node upgrades
[04:24] Q: How many of the advancements are customer or internally driven?
[05:43] Q: What do A16 and SPR bring to the table?
[08:07] Q: Does adding SPR increase cost per transistor?
[08:37] Q: Are A16 and SPR a package deal?
[09:15] Q: Where in the development cycle are A16 & SPR?
[10:16] Q: How different is NanoFlex from FinFlex?
[12:37] Q: How is the scale up of CoWoS progressing?
[15:59] Q: How do you plan to cool these massive chips?
[16:47] Q: When are you expecting SoW to be in production?
[17:08] Q: Due to new optics shrinking reticle sizes, will you reduce this too?
[17:32] Q: What are the current limits in semiconductors?
[18:59] Q: What is TSMC COUPE?
[21:33] Q: Which approach is best in optical?
[22:24] Q: Does TSMC have any plans for pluggable optics?
[23:15] Q: What are TSMC's plans for High-NA EUV?
[25:06] Q: How are the plans for the fab expansions going?
[26:48] Q: Does that extend to packaging?
[27:08] Q: What effects has the AI Boom had on your R&D decisions?
[28:15] Wrap-up
[29:07] Outro
Written version: open.substack.com/pub/morethanmoore/p/q-and-a-with-tsmc-on-next-gen-foundry
-----------------------
Need POTATO merch? There's a chip for that!
merch.techtechpotato.com
more-moore.com : Sign up to the More Than Moore Newsletter
patreon.com/TechTechPotato : Patreon gets you access to the TTP Discord server!
Follow Ian on Twitter at twitter.com/IanCutress
Follow TechTechPotato on Twitter at twitter.com/TechTechPotato
If you're in the market for something from Amazon, please use the following links. TTP may receive a commission if you purchase anything through these links.
Amazon USA : geni.us/AmazonUS-TTP
Amazon UK : geni.us/AmazonUK-TTP
Amazon CAN : geni.us/AmazonCAN-TTP
Amazon GER : geni.us/AmazonDE-TTP
Amazon Other : geni.us/TTPAmazonOther
Ending music: youtube.com/watch?v=2N0tmgau5E4
-----------------------
Welcome to the TechTechPotato (c) Dr. Ian Cutress
Ramblings about things related to Technology from an analyst for More Than Moore
#tsmc #a16 #bspdn
------------
More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Armari, ASM, Ayar Labs, BCG, Baidu, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NordPass, NVIDIA, ProteanTecs, Qualcomm, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.
![[36] TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA](https://i.ytimg.com/vi/WgJnzygxBk0/hqdefault.jpg "[36] TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA
Over the past year, I’ve had the chance to quiz every major foundry about their plans for the future. The latest in this series is TSMC, as part of their recent announcements around their roadmaps and upcoming process node technologies. As the world’s leading manufacturer of leading edge and EUV-based logic, as well as packaging the vast majority of the big AI chips, the pressure on TSMC to execute at speed and scale has only increased over the last few years. As part of their commitments to next-generation technologies, the company announced its A16 process node, Super Power Rail (the marketing name for its backside power delivery), ventures into co-packaged optics, and Silicon-on-Wafer technology, leveraging a demand for bigger substrates for the biggest chips. Here’s my latest video on these announcements.
https://www.youtube.com/watch?v=isjeYKLBffs
These announcements were made at TSMC’s US Technology Symposium earlier this year. The symposium is a roadshow, covering continents and key markets for the company. Just before the EU Symposium, I had a chance to catch up with Dr. Kevin Zhang, SVP and Deputy Co-COO of TSMC for an interview. We covered a wide range of topics, from Kevin’s thoughts on Moore’s Law, to how the market has changed under the weight of AI (also, the activations of AI).
[00:00] Intro
[00:48] Q: Is Moores Law Dead?
[02:11] Q: The utility of incremental manufacturing nodes
[03:37] Q: Customers leveraging node upgrades
[04:24] Q: How many of the advancements are customer or internally driven?
[05:43] Q: What do A16 and SPR bring to the table?
[08:07] Q: Does adding SPR increase cost per transistor?
[08:37] Q: Are A16 and SPR a package deal?
[09:15] Q: Where in the development cycle are A16 & SPR?
[10:16] Q: How different is NanoFlex from FinFlex?
[12:37] Q: How is the scale up of CoWoS progressing?
[15:59] Q: How do you plan to cool these massive chips?
[16:47] Q: When are you expecting SoW to be in production?
[17:08] Q: Due to new optics shrinking reticle sizes, will you reduce this too?
[17:32] Q: What are the current limits in semiconductors?
[18:59] Q: What is TSMC COUPE?
[21:33] Q: Which approach is best in optical?
[22:24] Q: Does TSMC have any plans for pluggable optics?
[23:15] Q: What are TSMCs plans for High-NA EUV?
[25:06] Q: How are the plans for the fab expansions going?
[26:48] Q: Does that extend to packaging?
[27:08] Q: What effects has the AI Boom had on your R&D decisions?
[28:15] Wrap-up
[29:07] Outro
Written version: https://open.substack.com/pub/morethanmoore/p/q-and-a-with-tsmc-on-next-gen-foundry
Need POTATO merch? Theres a chip for that!
http://merch.techtechpotato.com
http://more-moore.com : Sign up to the More Than Moore Newsletter
https://www.patreon.com/TechTechPotato : Patreon gets you access to the TTP Discord server!
Follow Ian on Twitter at http://twitter.com/IanCutress
Follow TechTechPotato on Twitter at http://twitter.com/TechTechPotato
If youre in the market for something from Amazon, please use the following links. TTP may receive a commission if you purchase anything through these links.
Amazon USA : https://geni.us/AmazonUS-TTP
Amazon UK : https://geni.us/AmazonUK-TTP
Amazon CAN : https://geni.us/AmazonCAN-TTP
Amazon GER : https://geni.us/AmazonDE-TTP
Amazon Other : https://geni.us/TTPAmazonOther
Ending music: https://www.youtube.com/watch?v=2N0tmgau5E4
Welcome to the TechTechPotato (c) Dr. Ian Cutress
Ramblings about things related to Technology from an analyst for More Than Moore
#tsmc #a16 #bspdn
More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on the More Than Moore newsletter or TechTechPotato YouTube channel and related social media. The companies that fall under this banner include AMD, Applied Materials, Armari, ASM, Ayar Labs, BCG, Baidu, Dialectica, Facebook, GLG, Guidepoint, IBM, Impala, Infineon, Intel, Kuehne+Nagel, Lattice Semi, Linode, MediaTek, NordPass, NVIDIA, ProteanTecs, Qualcomm, SiFive, SIG, SiTime, Supermicro, Synopsys, Tenstorrent, Third Bridge, TSMC, Untether AI, Ventana Micro.")
![[24b] Jim Keller Interview 2: AI Hardware on PCIe Cards](https://i.ytimg.com/vi/YOiXomG9FhE/hqdefault.jpg "[24b] Jim Keller Interview 2: AI Hardware on PCIe Cards
[24b] Jim Keller Interview 2: AI Hardware on PCIe Cards")
