Name: stable and unstable system | invertible & non invertible systems | Signals and Systems | Lec -16 @education4uofficial
Uploaded: 2026-09-19T08:17:00-05:00
Duration: 8 min 17 s
Description: stable and unstable system | invertible & non invertible systems | Signals and Systems | Lec -16

stable and unstable system | invertible & non invertible systems | Signals and Systems | Lec -16

Education 4u 2026-09-19 | stable and unstable system | invertible & non invertible systems | Signals and Systems | Lec -16

VHDL code for 4X1 multiplexer | dataflow model | Digital Systems Design | Lec-45

Education 4u 2024-10-20 | Digital Systems Design - VHDL
4X1 multiplexer VHDL code in dataflow model

Lec-44 : youtu.be/bUHl2X4bxc0

VHDL code Multiplexer | 2x1 4x1 | Dataflow & Behavioral model | Digital Systems Design | Lec-44

Education 4u 2024-10-19 | Digital Systems Design - VHDL
VHDL code 2x1 mux in dataflow model and behavioral model

Lec-43 : youtu.be/f9W9_SpMht8
Lec-45 : youtu.be/N5O0rmADBk0

Multiplexer | 4x1, 2x1 | Logic diagram | Digital Systems Design | Lec-43

Education 4u 2024-10-18 | Digital Systems Design - VHDL
Logic diagram 4x1, 2x1

Lec-42 : youtu.be/f4QXLoRoBwg
Lec-44 : youtu.be/bUHl2X4bxc0

VHDL code for BCD Adder | Digital Systems Design | Lec-42

Education 4u 2024-10-17 | Digital Systems Design - VHDL
bcd adder vhdl code

Lec-41 : youtu.be/GPAa0Uq4NGI
Lec-43 : youtu.be/f9W9_SpMht8

BCD adder | 4-bit | Circuit design | Digital Systems Design | Lec-41

Education 4u 2024-10-16 | Digital Systems Design - VHDL
circuit design 4-BCD adder

Lec-40 : youtu.be/V8au3dDW6zo
Lec-42 : youtu.be/f4QXLoRoBwg

If else in verilog | Syntax, Example & Wire statement | Digital Systems Design | Lec-30

Education 4u 2024-10-15 | Digital Systems Design - VHDL
If else in verilog - Syntax, Example & Wire statement

Lec-29 : youtu.be/PXB-04o1iwE
Lec-31 : youtu.be/88wDhqePP4Y

Module statement | Syntax |Types | Digital Systems Design | Lec-29

Education 4u 2024-10-14 | Digital Systems Design - VHDL
Module statement
Input - Output declaration syntax

Lec-28 : youtu.be/_v7vHCim-R0
Lec-30 : youtu.be/Bzyq84kvGQ8

VHDL Data Operators | Part-4/4 | Shift & Conditional | Digital Systems Design | Lec-28

Education 4u 2024-10-13 | Digital Systems Design - VHDL
Data Operators Part-4
Shift, Conditional & Concatenation

Lec-27 : youtu.be/F3EoDQBj_V4
Lec-29 : youtu.be/PXB-04o1iwE

VHDL Data Operators | Part-3/4 | Logical & Relational | Digital Systems Design | Lec-27

Education 4u 2024-10-12 | Digital Systems Design - VHDL
Logical & Relational Data Operators

Lec-26 : youtu.be/9kZEV9VbkCw
Lec-28 : youtu.be/_v7vHCim-R0

VHDL Data Operators | Part-2/4 | Bitwise & Reduction | Digital Systems Design | Lec-26

Education 4u 2024-10-11 | Digital Systems Design - VHDL
Bitwise & Reduction Data Operators

Lec-25 : youtu.be/wfmHkGqlND8
Lec-27 : youtu.be/F3EoDQBj_V4

VHDL Data Operators | Part-1/4 | Arithmetic | Digital Systems Design | Lec-25

Education 4u 2024-10-10 | Digital Systems Design - VHDL
Arithmetic Data Operators

Lec-24 : youtu.be/O_KJ_qwYhcY
Lec-26 : youtu.be/9kZEV9VbkCw

VHDL Data types | NET, Register | Digital Systems Design | Lec-24

Education 4u 2024-10-09 | Digital Systems Design - VHDL
Data types : NET, Register

Lec-23 : youtu.be/jJodM3JI-2U
Lec-25 : youtu.be/wfmHkGqlND8

Data flow and Behavioral modelling of verilog | Digital Systems Design | Lec-23

Education 4u 2024-10-08 | Digital Systems Design - VHDL
Data flow and Behavioral modelling of verilog

Lec-22 : youtu.be/PAHpMcd1tF4
Lec-24 : youtu.be/O_KJ_qwYhcY

Clocks | Ex1 | Reasoning shorts

Education 4u 2024-10-08 | Clocks
Reasoning shorts

Gate level modeling | Digital Systems Design | Lec-22

Education 4u 2024-10-07 | Digital Systems Design - VHDL
Gate level modeling

Lec-21 : youtu.be/HWV6HdLgZOw
Lec-23 : youtu.be/jJodM3JI-2U

Calendar | Ex2 | Reasoning shorts

Education 4u 2024-10-07 | Calendar
Reasoning shorts

Verilog | Introduction | Digital Systems Design | Lec-21

Education 4u 2024-10-06 | Digital Systems Design - VHDL
Introduction to Verilog

Lec-20 : youtu.be/sjUh1nr9ye0
Lec-22 : youtu.be/PAHpMcd1tF4

Number Analogy | Ex2 | Reasoning shorts

Education 4u 2024-10-05 | Number Analogy
Reasoning shorts

Packages in VHDL | Declaration | Digital Systems Design | Lec-20

Education 4u 2024-10-05 | Digital Systems Design - VHDL
VHDL Packages - Declaration

Lec-19 : youtu.be/lhjxAYqhsP8
Lec-21 : youtu.be/HWV6HdLgZOw

VHDL data types I STD LOGIC | Signed & Unsigned | Digital Systems Design | Lec-19

Education 4u 2024-10-05 | Digital Systems Design - VHDL data types
STD LOGIC - Signed & Unsigned data types

Lec-18 : youtu.be/BgqQmb2AENs
Lec-20 : youtu.be/sjUh1nr9ye0

Mathematical Operations | Ex2 Reasoning shorts

Education 4u 2024-10-05 | Mathematical Operations
Reasoning shorts

Probability | Ex2 | Aptitude shorts

Education 4u 2024-10-04 | Probability
Aptitude shorts

Carry look ahead adder | VHDL code | Digital Digital Systems Design | Lec - 40

Education 4u 2024-10-03 | Digital Systems Design
VHDL code for carry look ahead adder

Lec-39 : youtu.be/kVo3J2ED8ss
Lec-41 : youtu.be/GPAa0Uq4NGI

Carry look ahead adder | Part-2/2 | Digital Systems Design | Lec-39

Education 4u 2024-10-03 | Digital Systems Design - VHDL
Carry look ahead adder -2
Logic Diagram

Lec-38 : youtu.be/Gjj1BXjUkwM
Lec-40 : youtu.be/V8au3dDW6zo

Carry look ahead adder | Part-1/2 | Digital Systems Design | Lec-38

Education 4u 2024-10-02 | Digital Systems Design - VHDL
Carry look ahead adder -1
Introduction & Truth table

Lec-37 : youtu.be/v4Ehlny3TZk
Lec-39 : youtu.be/kVo3J2ED8ss

Binary adder and sub tractor | Block Diagram | Digital Systems Design | Lec-37

Education 4u 2024-09-30 | Digital Systems Design - VHDL
Binary adder and subtractor - Block Diagram

Lec-36 : youtu.be/q0kFg8kESQM
Lec-38 : youtu.be/Gjj1BXjUkwM

Parallel binary adder | RCA | FA | VHDL code |Digital Systems Design | Lec-36

Education 4u 2024-09-30 | Digital Systems Design - VHDL
VHDL code for parallel binary adder
Structural code for 4-bit RCA
VHDL code for FA

Lec-35 : youtu.be/bA0b6bnHa5w
Lec-37 : youtu.be/v4Ehlny3TZk

Parallel binary adder | Block Diagram | Digital Systems Design | Lec-35

Education 4u 2024-09-29 | Digital Systems Design - VHDL
Parallel binary adder : HA, FA
Block Diagram

Lec-34 : youtu.be/6JK0dwjCZ3U
Lec-36 : youtu.be/q0kFg8kESQM

Sub programs | Procedures & Functions | VHDL | Digital Systems Design | Lec-34

Education 4u 2024-09-28 | Digital Systems Design - VHDL
Sub programs : Procedures & Functions

Lec-33 : youtu.be/6vvNODkFlAw
Lec-35 : youtu.be/bA0b6bnHa5w

Ring counter | STLD shorts

Education 4u 2024-09-27 | STLD shorts
Ring counter

VHDL and Verilog languages | Comparison | Digital Systems Design | Lec-33

Education 4u 2024-09-27 | Digital Systems Design - VHDL
Comparison of VHDL and Verilog languages

Lec-32 : youtu.be/qGu_kBllnM8
Lec-34 : youtu.be/6JK0dwjCZ3U

Loop statements | for, while & Loop | Digital Systems Design | Lec-32

Education 4u 2024-09-26 | Digital Systems Design - VHDL
Loop statements : Syntax
for, while & Loop with examples

Lec-31 : youtu.be/88wDhqePP4Y
Lec-33 : youtu.be/6vvNODkFlAw

Gunn effect diode | Modes of operation | MWE

Education 4u 2024-09-26 | Microwave Engg
Modes of operation of Gunn effecct diode

VHDL | Wait, case and Null statement | Digital Systems Design | Lec-31

Education 4u 2024-09-25 | Digital Systems Design - VHDL
Wait, case and Null statements
Syntax & Examples

Lec-30 :youtu.be/Bzyq84kvGQ8
Lec-32 : youtu.be/qGu_kBllnM8

BCD to seven segment display | Decoder | STLD

Education 4u 2024-09-25 | STLD shorts
BCD to seven segment display decoder

Piezo electric transducer | EIM shorts

Education 4u 2024-09-19 | EIM shorts | Piezo electric transducer

Logic circuits | STLD shorts

Education 4u 2024-09-18 | Logic circuits
STLD shorts

Microwave solid state devices | Introduction | MWE shorts

Education 4u 2024-09-16 | Introduction to microwave solid state devices
MWE shorts

CRO | Block diagram | EIM shorts

Education 4u 2024-09-16 | Block diagram of CRO
EIM shorts

S matrix parameters | MWE shorts

Education 4u 2024-09-15 | S matrix parameters
MWE shorts

Maxwells bridge | EIM shorts

Education 4u 2024-09-14 | Maxwell's bridge
EIM shorts

K map | STLD shorts

Education 4u 2024-09-13 | Karnaugh's map | STLD

Waveguide discontinuities | MWE shorts

Education 4u 2024-09-10 | Waveguide discontinuities | MWE

Lissajous patterns | EIM shorts

Education 4u 2024-09-09 | Lissajous patterns | EIM shorts

Microwave Engineering | Introduction | MWE | shorts

Education 4u 2024-09-08 | MWE Shorts
Introduction to Microwave Engineering

Logic gates | STLD | Shorts

Education 4u 2024-09-07 | STLD shorts
Logic gates

Basic meter, DC Ammeter | EIM | Shorts

Education 4u 2024-09-06 | EIM Shorts
Basic meter, DC Ammeter

designing of synchronous sequential circuits | using state diagram | STLD | Lec-142

Education 4u 2024-09-03 | STLD : Switching Theory and Logic Design
Designing the synchronous sequential circuits using state diagram

Lec-141 : youtu.be/Tyd4TlRcaNQ

Reduction of state table and state Diagram STLD | Lec-141

Education 4u 2024-09-01 | STLD : Switching Theory and Logic Design
Reduction of state table & State Diaagram

Lec-140 : youtu.be/LJrBucIX1Zw
Lec-142 : youtu.be/ZKXMQ0XT-VU

Synchronous sequential circuits | Synthesis | STLD | Lec-140

Education 4u 2024-08-31 | STLD : Switching Theory and Logic Design
Synthesis of synchronous sequential circuits

Lec-139 : youtu.be/cBXhsbi1FSs
Lec-141 : youtu.be/Tyd4TlRcaNQ