VDHL code for SR Flip flop | Behavioral model | Digital Systems Design | Lec-77 Education 4u 2026-09-20 | VDHL code for SR Flip flop | Behavioral model | Digital Systems Design | Lec-77
VHDL code for 4X1 multiplexer | dataflow model | Digital Systems Design | Lec-45 Education 4u 2024-10-20 | Digital Systems Design - VHDL4X1 multiplexer VHDL code in dataflow model Lec-44 : youtu.be/bUHl2X4bxc0
VHDL code Multiplexer | 2x1 4x1 | Dataflow & Behavioral model | Digital Systems Design | Lec-44 Education 4u 2024-10-19 | Digital Systems Design - VHDLVHDL code 2x1 mux in dataflow model and behavioral model Lec-43 : youtu.be/f9W9_SpMht8Lec-45 : youtu.be/N5O0rmADBk0
Multiplexer | 4x1, 2x1 | Logic diagram | Digital Systems Design | Lec-43 Education 4u 2024-10-18 | Digital Systems Design - VHDLLogic diagram 4x1, 2x1 Lec-42 : youtu.be/f4QXLoRoBwgLec-44 : youtu.be/bUHl2X4bxc0
VHDL code for BCD Adder | Digital Systems Design | Lec-42 Education 4u 2024-10-17 | Digital Systems Design - VHDL bcd adder vhdl codeLec-41 : youtu.be/GPAa0Uq4NGILec-43 : youtu.be/f9W9_SpMht8
BCD adder | 4-bit | Circuit design | Digital Systems Design | Lec-41 Education 4u 2024-10-16 | Digital Systems Design - VHDLcircuit design 4-BCD adder Lec-40 : youtu.be/V8au3dDW6zoLec-42 : youtu.be/f4QXLoRoBwg
If else in verilog | Syntax, Example & Wire statement | Digital Systems Design | Lec-30 Education 4u 2024-10-15 | Digital Systems Design - VHDLIf else in verilog - Syntax, Example & Wire statementLec-29 : youtu.be/PXB-04o1iwELec-31 : youtu.be/88wDhqePP4Y
Module statement | Syntax |Types | Digital Systems Design | Lec-29 Education 4u 2024-10-14 | Digital Systems Design - VHDLModule statementInput - Output declaration syntaxLec-28 : youtu.be/_v7vHCim-R0Lec-30 : youtu.be/Bzyq84kvGQ8
VHDL Data Operators | Part-4/4 | Shift & Conditional | Digital Systems Design | Lec-28 Education 4u 2024-10-13 | Digital Systems Design - VHDLData Operators Part-4Shift, Conditional & Concatenation Lec-27 : youtu.be/F3EoDQBj_V4Lec-29 : youtu.be/PXB-04o1iwE
VHDL Data Operators | Part-3/4 | Logical & Relational | Digital Systems Design | Lec-27 Education 4u 2024-10-12 | Digital Systems Design - VHDLLogical & Relational Data OperatorsLec-26 : youtu.be/9kZEV9VbkCwLec-28 : youtu.be/_v7vHCim-R0
VHDL Data Operators | Part-2/4 | Bitwise & Reduction | Digital Systems Design | Lec-26 Education 4u 2024-10-11 | Digital Systems Design - VHDLBitwise & Reduction Data OperatorsLec-25 : youtu.be/wfmHkGqlND8Lec-27 : youtu.be/F3EoDQBj_V4
VHDL Data Operators | Part-1/4 | Arithmetic | Digital Systems Design | Lec-25 Education 4u 2024-10-10 | Digital Systems Design - VHDLArithmetic Data OperatorsLec-24 : youtu.be/O_KJ_qwYhcYLec-26 : youtu.be/9kZEV9VbkCw
VHDL Data types | NET, Register | Digital Systems Design | Lec-24 Education 4u 2024-10-09 | Digital Systems Design - VHDLData types : NET, RegisterLec-23 : youtu.be/jJodM3JI-2ULec-25 : youtu.be/wfmHkGqlND8
Data flow and Behavioral modelling of verilog | Digital Systems Design | Lec-23 Education 4u 2024-10-08 | Digital Systems Design - VHDLData flow and Behavioral modelling of verilogLec-22 : youtu.be/PAHpMcd1tF4Lec-24 : youtu.be/O_KJ_qwYhcY
Gate level modeling | Digital Systems Design | Lec-22 Education 4u 2024-10-07 | Digital Systems Design - VHDLGate level modelingLec-21 : youtu.be/HWV6HdLgZOwLec-23 : youtu.be/jJodM3JI-2U
Verilog | Introduction | Digital Systems Design | Lec-21 Education 4u 2024-10-06 | Digital Systems Design - VHDLIntroduction to VerilogLec-20 : youtu.be/sjUh1nr9ye0Lec-22 : youtu.be/PAHpMcd1tF4
Packages in VHDL | Declaration | Digital Systems Design | Lec-20 Education 4u 2024-10-05 | Digital Systems Design - VHDLVHDL Packages - DeclarationLec-19 : youtu.be/lhjxAYqhsP8Lec-21 : youtu.be/HWV6HdLgZOw
VHDL data types I STD LOGIC | Signed & Unsigned | Digital Systems Design | Lec-19 Education 4u 2024-10-05 | Digital Systems Design - VHDL data typesSTD LOGIC - Signed & Unsigned data typesLec-18 : youtu.be/BgqQmb2AENsLec-20 : youtu.be/sjUh1nr9ye0
Mathematical Operations | Ex2 Reasoning shorts Education 4u 2024-10-05 | Mathematical Operations Reasoning shorts
Carry look ahead adder | VHDL code | Digital Digital Systems Design | Lec - 40 Education 4u 2024-10-03 | Digital Systems DesignVHDL code for carry look ahead adderLec-39 : youtu.be/kVo3J2ED8ssLec-41 : youtu.be/GPAa0Uq4NGI
Carry look ahead adder | Part-2/2 | Digital Systems Design | Lec-39 Education 4u 2024-10-03 | Digital Systems Design - VHDLCarry look ahead adder -2Logic DiagramLec-38 : youtu.be/Gjj1BXjUkwMLec-40 : youtu.be/V8au3dDW6zo
Carry look ahead adder | Part-1/2 | Digital Systems Design | Lec-38 Education 4u 2024-10-02 | Digital Systems Design - VHDLCarry look ahead adder -1Introduction & Truth tableLec-37 : youtu.be/v4Ehlny3TZkLec-39 : youtu.be/kVo3J2ED8ss
Binary adder and sub tractor | Block Diagram | Digital Systems Design | Lec-37 Education 4u 2024-09-30 | Digital Systems Design - VHDLBinary adder and subtractor - Block DiagramLec-36 : youtu.be/q0kFg8kESQMLec-38 : youtu.be/Gjj1BXjUkwM
Parallel binary adder | RCA | FA | VHDL code |Digital Systems Design | Lec-36 Education 4u 2024-09-30 | Digital Systems Design - VHDLVHDL code for parallel binary adderStructural code for 4-bit RCAVHDL code for FALec-35 : youtu.be/bA0b6bnHa5wLec-37 : youtu.be/v4Ehlny3TZk
Parallel binary adder | Block Diagram | Digital Systems Design | Lec-35 Education 4u 2024-09-29 | Digital Systems Design - VHDLParallel binary adder : HA, FABlock DiagramLec-34 : youtu.be/6JK0dwjCZ3ULec-36 : youtu.be/q0kFg8kESQM
Sub programs | Procedures & Functions | VHDL | Digital Systems Design | Lec-34 Education 4u 2024-09-28 | Digital Systems Design - VHDLSub programs : Procedures & FunctionsLec-33 : youtu.be/6vvNODkFlAwLec-35 : youtu.be/bA0b6bnHa5w
VHDL and Verilog languages | Comparison | Digital Systems Design | Lec-33 Education 4u 2024-09-27 | Digital Systems Design - VHDLComparison of VHDL and Verilog languagesLec-32 : youtu.be/qGu_kBllnM8Lec-34 : youtu.be/6JK0dwjCZ3U
Loop statements | for, while & Loop | Digital Systems Design | Lec-32 Education 4u 2024-09-26 | Digital Systems Design - VHDLLoop statements : Syntaxfor, while & Loop with examplesLec-31 : youtu.be/88wDhqePP4YLec-33 : youtu.be/6vvNODkFlAw
Gunn effect diode | Modes of operation | MWE Education 4u 2024-09-26 | Microwave Engg Modes of operation of Gunn effecct diode
VHDL | Wait, case and Null statement | Digital Systems Design | Lec-31 Education 4u 2024-09-25 | Digital Systems Design - VHDLWait, case and Null statementsSyntax & ExamplesLec-30 :youtu.be/Bzyq84kvGQ8Lec-32 : youtu.be/qGu_kBllnM8
BCD to seven segment display | Decoder | STLD Education 4u 2024-09-25 | STLD shortsBCD to seven segment display decoder
Piezo electric transducer | EIM shorts Education 4u 2024-09-19 | EIM shorts | Piezo electric transducer
Microwave solid state devices | Introduction | MWE shorts Education 4u 2024-09-16 | Introduction to microwave solid state devicesMWE shorts
Microwave Engineering | Introduction | MWE | shorts Education 4u 2024-09-08 | MWE ShortsIntroduction to Microwave Engineering
designing of synchronous sequential circuits | using state diagram | STLD | Lec-142 Education 4u 2024-09-03 | STLD : Switching Theory and Logic DesignDesigning the synchronous sequential circuits using state diagram Lec-141 : youtu.be/Tyd4TlRcaNQ
Reduction of state table and state Diagram STLD | Lec-141 Education 4u 2024-09-01 | STLD : Switching Theory and Logic DesignReduction of state table & State DiaagramLec-140 : youtu.be/LJrBucIX1ZwLec-142 : youtu.be/ZKXMQ0XT-VU
Synchronous sequential circuits | Synthesis | STLD | Lec-140 Education 4u 2024-08-31 | STLD : Switching Theory and Logic DesignSynthesis of synchronous sequential circuits Lec-139 : youtu.be/cBXhsbi1FSsLec-141 : youtu.be/Tyd4TlRcaNQ
