Uploaded January 2021 | Updated September 2026, 2 weeks ago

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This program calculates 75/5 using a repeated subtraction algorithm that utilises the hardware counter.
It takes 23 clock cycles (16.1 seconds) for 75/5. (as opposed to 37 cycles without the counter)

In theory the hardware counter doubles the speed of division by repeated subtraction, but it requires a little more setup before the main loop.
The speed increase from the hardware counter comes from the ability to increment the counter at the same time as doing subtraction with the main ALU. This allows the ALU to focus 100% on subtraction without having to increment the answer.

MPU5.0 Specs:
7 tick clock speed (0.7 seconds)
3 stage pipe (with dual instruction fetching to speed up conditional instructions)
8 bit word length
uses a custom version of VLIW arch
9 general purpose registers
32 bytes of RAM
128 word instruction ROM (split into 2 lots of 64 for dual fetching)
8 bit hardware multiplier