Uploaded January 2021 | Updated September 2026, 2 weeks ago
This program takes 35 clock cycles (24.5 seconds) to do 15x15 by repeated addition.
15x15 = 225 if that wasn't obvious lol
Multiplication by repeated addition is very slow, shift and add would be faster. Shift and add will be done in another video.
MPU5.0 Specs:
7 tick clock speed (0.7 seconds)
3 stage pipe (with dual instruction fetching to speed up conditional instructions)
8 bit word length
uses a custom version of VLIW arch
9 general purpose registers
32 bytes of RAM
128 word instruction ROM (split into 2 lots of 64 for dual fetching)
8 bit hardware multiplier
This program takes 35 clock cycles (24.5 seconds) to do 15x15 by repeated addition.
15x15 = 225 if that wasn't obvious lol
Multiplication by repeated addition is very slow, shift and add would be faster. Shift and add will be done in another video.
MPU5.0 Specs:
7 tick clock speed (0.7 seconds)
3 stage pipe (with dual instruction fetching to speed up conditional instructions)
8 bit word length
uses a custom version of VLIW arch
9 general purpose registers
32 bytes of RAM
128 word instruction ROM (split into 2 lots of 64 for dual fetching)
8 bit hardware multiplier
![MPU 7 Pong (zero player) [ 2 Hz Minecraft Redstone CPU ]](https://i.ytimg.com/vi/d_4M1oLuxKE/mqdefault.jpg "MPU 7 Pong (zero player) [ 2 Hz Minecraft Redstone CPU ]
The MPU 7 is my latest and fastest Minecraft Redstone CPU.
This video is at 6x speed and the carpet mod tick speed is set to 2 times speed.
In this program the ball bounces around the screen while a non-player controlled paddle follows it.
Since it took about 9 seconds per frame, you wouldnt want to play this in real time lol.
Join the URCL (Universal Reduced Computer Language) discord:
https://discord.gg/Nv8jzWg5j8
MPU 7 Specs:
• No command blocks or pistons
• 2 Hz clock speed (5 ticks or 0.5 seconds per clock pulse)
• 5 stage waterfall pipeline (Fetch1 - Fetch2 - Decode - Execute - Writeback)
• 10 general purpose simulated dual read registers (with no read before write hazards because of the automatic forwarding)
• 8 bit word length
• 256 word instruction ROM x2
• 32 bit instruction length (that includes an 8 bit immediate value)
• VLIW architecture
• 32 bit hardware BCD converter
• 8 bit hardware multiplier
• 8 bit hardware divider
• 8 bit RNG
• 64x32 pixel display (1x1 pixels) which can be shifted upwards 8 pixels whenever needed
• 1 frame buffer
• Full qwerty keyboard with arrow keys and function keys for user input
• 128 bytes of main RAM
• 256 bytes of screen RAM
• Up to 128 I/O ports
• External 8 kiB paging ROM for storing large amounts of data (Like Bad Apple!!)
• 7 testable flags
• Full 7 bit character set (a custom one, so not ASCII) which uses 4x8 characters
• Can be started, stopped and reset from the UI
• Almost fully compatible with URCL
MPU 7 ISA:
https://docs.google.com/spreadsheets/d/1fgXPalCBTGg-X3QGXmNagxAMHoiOW_9nbOgaJl7fFoY/edit?usp=sharing
MPU 7 World download is available in the URCL discord:
https://discord.gg/Nv8jzWg5j8
If you want to support me creating these videos, Patreon is:
https://www.patreon.com/modpunchtree
or my PayPal link is:
https://paypal.me/modpunchtree")
![MPU 8 Super Cool Program ! [ 3.3 Hz Minecraft Redstone CPU ]](https://i.ytimg.com/vi/dveDtGN2nJA/mqdefault.jpg "MPU 8 Super Cool Program ! [ 3.3 Hz Minecraft Redstone CPU ]
The MPU 8 is my latest and fastest Minecraft Redstone CPU.
This program simply prints text on the screen which is stored in the external ROM. This was done to test the external ROM to make sure it works.
This video has not been sped up but the tick speed has been set to 18 times speed. (so a net speed up of 18 times)
Join the URCL (Universal Reduced Computer Language) discord:
https://discord.gg/Nv8jzWg5j8
MPU 8 Specs:
• No command blocks or pistons
• 3.3 Hz clock speed (3 ticks or 0.3 seconds per clock pulse)
• 9 stage waterfall pipeline
• 12 general purpose simulated dual read registers (with automatic forwarding at 6 ticks)
• 8 bit word length
• 256 word instruction ROM x2
• 32 bit instruction length (that includes an 8 bit immediate value)
• VLIW architecture
• 32 bit hardware BCD converter
• 8 bit hardware multiplier
• 8 bit hardware divider
• 64x64 pixel display which can be shifted upwards 8 pixels whenever needed
• 1 frame buffer
• Full qwerty keyboard with arrow keys and function keys for user input
• 128 bytes of main RAM
• 512 bytes of screen RAM
• Up to 128 I/O ports
• External 8 kiB paging ROM for storing large amounts of data
• 13 testable flags
• 8 bit character set (a custom one, so not ASCII) which uses 4x8 characters
• Can be started, stopped and reset from the UI
• Almost fully compatible with URCL
MPU 8 ISA:
https://docs.google.com/spreadsheets/d/1KRoZNu5ic36-vcP-6llN8L27ZvLxW5ILiaOX5gcoAC4/edit?usp=sharing
If you want to support me creating these videos, my Patreon is:
https://www.patreon.com/modpunchtree
or my PayPal link is:
https://paypal.me/modpunchtree")
![3D Rotating Cube !! [ MPU 8 | 3.3 Hz Minecraft Redstone CPU ]](https://i.ytimg.com/vi/epuTvLgKYbE/mqdefault.jpg "3D Rotating Cube !! [ MPU 8 | 3.3 Hz Minecraft Redstone CPU ]
The MPU 8 is my latest and fastest Minecraft Redstone CPU.
Here the MPU 8 is rendering a 3D cube and rotating it.
The matrix multiplications for calculating the rotation and rasterisation of the cube are all being calculated each frame by the CPU.
This is NOT a video and it does NOT use precalculated points - the positions of the points are ALL calculated on the CPU.
For trigonometry i simplified it a lot by assuming that Sin(x) = x and Cos(x) = 1 where x is a small angle, this gives an approximation that is good enough for a couple minutes.
In this program the cube becomes more distorted as time progresses due to the rounding errors building up from the division operations as well as the trigonometry assumption.
(this is why the cube looks quite twisted and stretched towards the end)
This video been sped up 8x and the tick speed has been set to 800 times speed (so a total speed up of 6400x).
Join the URCL (Universal Reduced Computer Language) discord:
https://discord.gg/Nv8jzWg5j8
MPU 8 Specs:
• No command blocks or pistons
• 3.3 Hz clock speed (3 ticks or 0.3 seconds per clock pulse)
• 9 stage waterfall pipeline
• 12 general purpose simulated dual read registers (with automatic forwarding at 6 ticks)
• 8 bit word length
• 256 word instruction ROM x2
• 32 bit instruction length (that includes an 8 bit immediate value)
• VLIW architecture
• 32 bit hardware BCD converter
• 8 bit hardware multiplier
• 8 bit hardware divider
• 64x64 pixel display which can be shifted upwards 8 pixels whenever needed
• 1 frame buffer
• Full qwerty keyboard with arrow keys and function keys for user input
• 128 bytes of main RAM
• 512 bytes of screen RAM
• Up to 128 I/O ports
• External 8 kiB paging ROM for storing large amounts of data
• 13 testable flags
• 8 bit character set (a custom one, so not ASCII) which uses 4x8 characters
• Can be started, stopped and reset from the UI
• Almost fully compatible with URCL
MPU 8 ISA:
https://docs.google.com/spreadsheets/d/1KRoZNu5ic36-vcP-6llN8L27ZvLxW5ILiaOX5gcoAC4/edit?usp=sharing
If you want to support me creating these videos, my Patreon is:
https://www.patreon.com/modpunchtree
or my PayPal link is:
https://paypal.me/modpunchtree")
![MPU 8 Fizzbuzz [ 3.3 Hz Minecraft Redstone CPU ]](https://i.ytimg.com/vi/g0mmNctz7w4/mqdefault.jpg "MPU 8 Fizzbuzz [ 3.3 Hz Minecraft Redstone CPU ]
The MPU 8 is my latest and fastest Minecraft Redstone CPU.
Here the MPU 8 is running a FizzBuzz program.
Where for each value:
if the value is divisible by 3 it prints Fizz,
else if the value is divisible by 5 it prints Buzz,
else if its divisible by both 3 and 5 it prints FizzBuzz,
else it prints the value itself in base 10.
This video has been sped up 2 times and the tick speed has been set to 10 times speed. (so a net speed up of 20 times)
This program took 732 cycles to run (12 minutes and 12 seconds at default Minecraft speed).
Join the URCL (Universal Reduced Computer Language) discord:
https://discord.gg/Nv8jzWg5j8
MPU 8 Specs:
• No command blocks or pistons
• 3.3 Hz clock speed (3 ticks or 0.3 seconds per clock pulse)
• 9 stage waterfall pipeline
• 12 general purpose simulated dual read registers (with automatic forwarding at 6 ticks)
• 8 bit word length
• 256 word instruction ROM x2
• 32 bit instruction length (that includes an 8 bit immediate value)
• VLIW architecture
• 32 bit hardware BCD converter
• 8 bit hardware multiplier
• 8 bit hardware divider
• 64x64 pixel display which can be shifted upwards 8 pixels whenever needed
• 1 frame buffer
• Full qwerty keyboard with arrow keys and function keys for user input
• 128 bytes of main RAM
• 512 bytes of screen RAM
• Up to 128 I/O ports
• External 8 kiB paging ROM for storing large amounts of data
• 13 testable flags
• 8 bit character set (a custom one, so not ASCII) which uses 4x8 characters
• Can be started, stopped and reset from the UI
• Almost fully compatible with URCL
MPU 8 ISA:
https://docs.google.com/spreadsheets/d/1KRoZNu5ic36-vcP-6llN8L27ZvLxW5ILiaOX5gcoAC4/edit?usp=sharing
If you want to support me creating these videos, my Patreon is:
https://www.patreon.com/modpunchtree
or my PayPal link is:
https://paypal.me/modpunchtree")
![MPU 7 - 16 bit Fibonacci [ 2 Hz Minecraft Redstone CPU ]](https://i.ytimg.com/vi/hEcQe8sO6x4/mqdefault.jpg "MPU 7 - 16 bit Fibonacci [ 2 Hz Minecraft Redstone CPU ]
The MPU 7 is my latest and fastest Minecraft redstone CPU.
To get the Fibonacci sequence, you simply add the previous 2 numbers together to calculate the next number - starting with 0 and 1.
The MPU 7 can calculate the next 16 bit number every 2 clock cycles (10 ticks or 1 second), if you ignoring converting the values to BCD and printing them to the display.
The video has been sped up to 2 times speed to make it less boring to watch and the tick rate has been sped up by carpet mod meaning it is running as fast as it can on my IRL computer.
Join the URCL (Universal Reduced Computer Language) discord:
https://discord.gg/Nv8jzWg5j8
MPU 7 Specs:
• No command blocks or pistons
• 2 Hz clock speed (5 ticks or 0.5 seconds per clock pulse)
• 5 stage waterfall pipeline (Fetch1 - Fetch2 - Decode - Execute - Writeback)
• 10 general purpose simulated dual read registers (with no read before write hazards because of the automatic forwarding)
• 8 bit word length
• 256 word instruction ROM x2
• 32 bit instruction length (that includes an 8 bit immediate value)
• VLIW architecture
• 32 bit hardware BCD converter
• 8 bit hardware multiplier
• 8 bit hardware divider
• 8 bit RNG
• 64x32 pixel display (1x1 pixels) which can be shifted upwards 8 pixels whenever needed
• 1 frame buffer
• Full qwerty keyboard with arrow keys and function keys for user input
• 128 bytes of main RAM
• 256 bytes of screen RAM
• Up to 128 I/O ports
• External 8 kiB paging ROM for storing large amounts of data
• 7 testable flags
• Full 7 bit character set (a custom one, so not ASCII) which uses 4x8 characters
• Can be started, stopped and reset from the UI
• Almost fully compatible with URCL
MPU 7 ISA:
https://docs.google.com/spreadsheets/d/1fgXPalCBTGg-X3QGXmNagxAMHoiOW_9nbOgaJl7fFoY/edit?usp=sharing
MPU 7 World download is available in the URCL discord:
https://discord.gg/Nv8jzWg5j8
If you want to support me creating these videos, my PayPal link is: https://paypal.me/modpunchtree")
